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DG221B New Product Vishay Siliconix Quad SPST CMOS Analog Switch with Latches FEATURES D D D D BENEFITS APPLICATIONS D D D D D D mP Based Systems Automatic Test Equipment Communication Systems Data Acquisition Systems Medical Instrumentation Factory Automation Accepts 150-ns Write Pulse Width D Compatible with Most mP Buses 5-V On-Chip Regulator D Allows Wide Power Supply Tolerance Without Affecting TTL Compatibility Latches Are Transparent with WR Low D Reduced Power Consumption Low On-Resistance: 60 W D Allows Flexibility of Design DESCRIPTION The DG221B is a monolithic quad single-pole, single-throw analog switch designed for precision switching applications in communication, instrumentation and process control systems. Featuring independent onboard latches and a common WR pin, each DG221B can be memory mapped, and addressed as a single data byte for simultaneous switching. The DG221B combines low power and low on-resistance (60 W typical) while handling continuous currents up to 20 mA. An epitaxial layer prevents latchup. The device features true bidirectional performance in the on condition. FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION Four Latchable SPST Switches per Package Dual-In-Line and SOIC TRUTH TABLE 16 15 14 IN2 D2 S2 V+ WR S3 D3 IN3 X X 1 IN1 D1 S1 V- GND S4 D4 IN4 1 2 3 Input Latch 4 5 6 7 8 INX 0 1 WR 0 0 Switch ON OFF Control data latched-in, switches on or off as selected by last INX Maintains previous state 13 12 11 10 9 Logic "0" v 0.8 V Logic "1" w 2.4 V ORDERING INFORMATION Temp Range Package 16-Pin Plastic DIP 16-Pin Narrow SOIC Part Number DG221BDJ DG221BDY Top View -40_C to 85_C _ _ Document Number: 71616 S-03627--Rev. A, 23-Apr-01 www.vishay.com 1 DG221B Vishay Siliconix New Product ABSOLUTE MAXIMUM RATINGS Voltages Referenced to V- V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2 V to (V+) +2 V or 20 mA, whichever occurs first Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D (Pulsed 1 ms, 10% duty cycle) . . . . . . . . . . . . . . 70 mA Storage Temperature: (DJ and DY Suffix) . . . . . . . . . . . -65 to 125_C Power Dissipation (Package)b 16-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 16-Pin SOICd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW Notes: a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 6.5 mW/_C above 25_C d. Derate 7.7 mW/_C above 75_C SCHEMATIC DIAGRAM (TYPICAL CHANNEL) V+ 5V Reg GND INX - + V- V+ WR - + V- Latch Level Shift/ Drive V+ S D V- FIGURE 1. www.vishay.com 2 Document Number: 71616 S-03627--Rev. A, 23-Apr-01 DG221B New Product SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Analog Switch Analog Signal Rangee Drain-Source On-Resistance Source Off Leakage Current Drain Off Leakage Current Drain On Leakage Current VANALOG rDS(on) IS(off) VS = "14 V, VD = #14 V " # ID(off) ID(on) VS = VD = "14 V IS = -10 mA, VD = "10 V Full Room Full Room Full Room Full Room Full -5 -100 -5 -100 -5 -200 -15 60 "0.01 "0.02 "0.01 15 90 135 5 100 5 100 5 200 nA V W Vishay Siliconix Limits -40 to 85_C Symbol V+ = 15 V, V- = -15 V VIN = 2.4 V, 0.8f V, WR = 0 Tempb Mind Typc Maxd Unit Digital Control Input Current IINL , IINH VIN = 0 V or = 2.4 V Room Full -1 -10 -0.0004 1 10 mA Dynamic Characteristics Turn-On Time Turn-Off Time Turn-On Time Write Turn-Off Time Write Write Pulse Width Input Setup Time Input Hold Time Charge Injection Source-Off Capacitance Drain-Off Capacitance Channel-On Capacitance Off Isolation Interchannel Crosstalk tON tOFF tON, WR tOFF, WR tW tS tH Q CS(off) CD(off) CD(on) OIRR XTALK VS = 1 Vp-p, f = 100 kHz CL = 15 pF, RL = 1 kW f = 1 MHz, VS, VD = 0 V CL = 1000 pF VGEN = 0 V, RGEN = 0 W See Figure 4 See Figure 3 Room See Figure 2 Room Room Room Room Room Room Room Room Room Room Room Room 150 180 20 120 130 18 20 8 9 29 70 90 dB pF pC 550 340 550 340 ns Power Supplies Positive Supply Current Negative Supply Current I+ I- All Channels On or Off VIN = 0 V or 2.4 V Full Room -1 0.8 -0.4 1.5 mA Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. Document Number: 71616 S-03627--Rev. A, 23-Apr-01 www.vishay.com 3 DG221B Vishay Siliconix TEST CIRCUITS +15 V New Product V+ 2V S IN GND WR V- RL 1 kW CL 35 pF D VO Logic Input 3V 50% 0V tr < 10 ns tf < 10 ns Switch Input Switch Output VS 90% VO tON tOFF -15 V CL (includes fixture and stray capacitance) VO = VS RL RL + rDS(on) FIGURE 2. Switching Time +15 V 0V WR 2V S IN GND V- RL 1 kW CL 35 pF VOUT -15 V CL (includes fixture and stray capacitance) VO = VS RL RL + rDS(on) FIGURE 3. WR Switching Time VO tON, WR tOFF , WR VS 90% V+ D VO IN 3V WR 0V 3V 0V tr < 10 ns tf < 10 ns 50% 3V 50% IN tS 3V 50% WR tW tH = Hold Time tS = Setup Time tW = WR Pulse Width tH tS tH VOUT The latches are level sensitive. When WR is held low the latches are transparent and the switches respond to the digital inputs. The digital inputs are latched on the rising edge of WR. FIGURE 4. WR Setup Conditions www.vishay.com 4 Document Number: 71616 S-03627--Rev. A, 23-Apr-01 DG221B New Product TEST CIRCUITS +15 V DVO Rg Vg 3V WR V- V+ S IN D VO CL 1000 pF VO Vishay Siliconix INX OFF ON OFF -15 V DVO = measured voltage error due to charge injection The charge injection in coulombs is Q = CL x DVO FIGURE 5. Charge Injection +15 V C C +15 V V+ V+ VS D VO Rg = 50 W 0V NC S1 IN1 S2 D1 50 W VS Rg = 50 W 2.4 V S IN GND WR V- C RL D2 RL GND WR V- C VO 0V -15 V IN2 Off Isolation = 20 log C = RF bypass VS VO -15 V XTALK Isolation = 20 log C = RF bypass VS VO FIGURE 6. Off Isolation FIGURE 7. Channel-to-Channel Crosstalk APPLICATION HINTSa V+ Positive Supply Voltage (V) 15 10 10 V- Negative Supply Voltage (V) -15 -10 -5 GND (V) 0 0 0 WR (V) 2.4/0.8 2.4/0.8 2.4/0.8 VIN Logic Input Voltage VINH(min)/VINL(max) (V) 2.4/0.8 2.4/0.8 2.4/0.8 VS or VD Analog Voltage Range (V) -15 to 15 -10 to 10 -5 to 10 Notes: a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing. Document Number: 71616 S-03627--Rev. A, 23-Apr-01 www.vishay.com 5 DG221B Vishay Siliconix APPLICATIONS +15 V VIN New Product V+ 9 MW S1 DG221B IN1 D C Q D1 S2 900 kW IN2 D C Q D2 90 kW Data Bus S3 IN3 D C Q D3 S4 9 kW IN4 WR WR GND CS Address Bus Address Decoder D C Q D4 V- 1 kW -15 V The TL081 is used as an output buffer while the voltage divider provides attenuation. + TL081 - VO FIGURE 8. mP-Controlled Analog Signal Attenuator TRUTH TABLE IN1 0 1 0 1 1 1 OUTPUT ATTENUATION FOR FIGURE 8 ON SWITCH All None 1 2 3 4 IN2 0 1 1 0 1 1 IN3 0 1 1 1 0 1 IN4 0 1 1 1 1 0 WRA 0 0 0 0 0 0 WR 0 0 0 0 IN1 0 1 1 1 IN2 1 0 1 1 IN3 1 1 0 1 IN4 1 1 1 0 Gain 0.1 0.01 0.001 0.0001 Notes: a. WR may be held at "0" for temporary operation similar to DG201A/DG201B. With WR at "0" SW1 will remain on as long as IN1 is held at "0". www.vishay.com Document Number: 71616 S-03627--Rev. A, 23-Apr-01 6 |
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